AI Lund Lunch seminar: Neuromorphic technology ? Rethinking the computer for AI

Published: 2025-12-15

Topic: Neuromorphic technology ? Rethinking the computer for AI

When: 11 March, 2026 12.00 to 13.00 CET

Where: Online - link by registration 

Speakers: 

• Mattias Borg, Electromagnetics and Nanoelectronics, Lund University
• Baktash Behmanesh, Integrated Sensors and Adaptive Technology for Sustainable Products and Manufacturing, Lund University

Abstract

Artificial Intelligence (AI) has revolutionized countless domains, but its growing energy footprint poses a critical challenge. The primary bottleneck lies in data movement - shuttling information between memory and processors consumes far more energy than computation itself. In contrast, the human brain achieves remarkable efficiency by computing where the data resides. Neuromorphic technology takes inspiration from this principle, rethinking the computer architecture to suit the heavy data loads of AI. By leveraging materials with memory properties, such as memristors, we can enable analog, in-memory computation that drastically reduces energy costs. 

This talk explores how neuromorphic hardware can disrupt conventional AI processing and why success will depend on a co-design approach, requiring interdisciplinary teams integrating expertise in materials science, circuits and system architecture, and algorithm development. 

We will outline our current effort (NeuTec) which will bring together Swedish neuromorphic researchers at all technology levels, bridging disciplines and forming common visions, with the ultimate goal for Sweden to lead in a new era of sustainable, brain-inspired computing. 

Speaker bios

Mattias Borg is Senior Lecturer in Nanoelectronics at Lund University, with previous research positions within the semiconductor industry, including IBM and Ericsson. His research focuses on the materials and device aspects of neuromorphic technology, as well as three-dimensional integration of emerging technologies with Si CMOS. 

Baktash Behmanesh received his PhD in 2017 from Sharif University of Technology, Tehran, Iran. In 2018, he joined the EIT department of Lund University, where he is currently an Associate Senior Lecturer focusing on analog/RF Integrated Circuit design. His research interests include RF and millimeter-wave front-end design, design of frequency synthesis circuits for wireless communication systems, and neuromorphic circuit design.

Registration

To participate is free of charge. Sign up at ai.lu.se/2026-03-11/registration and we send you an access link to the zoom platform.

AI Lund lunch seminar: Tracking drones by sound

Published: 2025-12-09

Topic: Tracking drones by sound

When: 4 March 12.00 to 13.00

Where: Online - link by registration

Speaker: Magnus Oskarsson, Mathematical Imaging Group, Lund University

Spoken language: English

Abstract

TBA

Registration

To participate is free of charge. 
Sign up at ai.lu.se/2026-03-04/registration and we send you an access link to the zoom platform.
 

Thesis defense: 3D Integration Technology and Near-Memory Computing for Edge AI

Published: 2025-11-27

Arturo Prieto defends his thesis "3D Integration Technology and Near-Memory Computing for Edge AI".

Link to thesis in LU Research Portal.

Zoom link.
Zoom ID: 66847927874.

Higher performance through increased technology integration has focused on scaling transistor dimensions. However, the manufacturing process is increasingly expensive and faces technical challenges in the development of new breakthroughs. Evaluation of the third dimension has emerged as a promising alternative to scaling, which enables stacking of semiconductor components with 3D interconnections. Different technologies present different integration strategies, where 3D sequential integration (3DSI) enables small pitch for 3D contacts, allowing for high-integration circuits. A library of standard cells has been designed and characterized according to 3DSI, enhancing the high-integration capabilities of the technology for digital designs. This library compiles the required predefined logic cells that can be used in the design of a digital integrated circuit (IC).

The design of ICs as a foundation for edge AI is focused on enhancing memory and computing resources to improve the processing capabilities of such platforms. Computing architectures are traditionally based on the concept of von Neumann architecture, which distinguishes computing and memory units as two independent entities. However, near-memory computing (NMC) is presented as a viable alternative to the von Neumann architecture that brings computation closer to memory. NMC is non-intrusive to the conventional low-level structure of SRAM and enhances memory bandwidth for hardware acceleration. The integration of accelerators into resource-constrained platforms has been evaluated, expanding the functionality with custom hardware tailored for computation-intensive AI workloads. Furthermore, flexibility has been achieved by providing modularity to the design architecture.

The proposed architectures are evaluated by programs that highlight the performance of integrated AI hardware accelerators into edge devices, emphasizing the importance of software and hardware co-design. The contributions of this thesis focus on 3DSI technology circuit design and NMC architectures evaluating performance, energy and area efficiency.

Thesis defense: Near-Memory Computing Architectures for Scalable Edge AI Applications

Published: 2025-11-10

Masoud Nouripayam defends his thesis "Near-Memory Computing Architectures for Scalable Edge AI Applications."

Zoom link.
Zoom ID: 69455644174

Link to the thesis i LU Research Portal.

Artificial intelligence (AI) and machine learning (ML) are rapidly permeating nearly every aspect of modern life, from personal devices and autonomous systems to industrial automation and environmental monitoring. The growing demand for intelligence at the network edge is reshaping how computing hardware is conceived and built. Edge AI platforms are expected to deliver high throughput within tight energy and area budgets, operate reliably at low voltages, and adapt to diverse workloads, while data movement between processors and memory continues to dominate system cost. These trends position memory-centric computing as a compelling alternative to conventional architectures. By tightly coupling local memory, approximate processing, and near-memory execution, this work advances the development of compact, high-throughput, and energy-efficient AI hardware.